ATMEGA649V-8MI【PDF 78/146 页】IC AVR MCU FLASH 64K 1.8V 64QFN

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Sheet目录1905

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PIC16(L)F1825/1829

DS41440C-page 320

2010-2012 Microchip Technology Inc.

26.5

EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

26.5.1

SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception (see

Section 26.4.2.4 “Synchronous Slave

Reception Setup:”

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

The RCIF interrupt flag must be cleared by

reading RCREG to unload any pending

characters in the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE, Global

Interrupt Enable, bit of the INTCON register is also set,

then the Interrupt Service Routine at address 004h will

be called.

26.5.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

RCSTA and TXSTA Control registers must be

configured for synchronous slave transmission

(see Section 26.4.2.2 “Synchronous Slave

Transmission Setup:”

The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

Interrupt enable bits TXIE of the PIE1 register and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

26.5.3

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default

locations are upon a Reset, see Section 12.1

“Alternate Pin Function”

for more information.

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